FSMD Functional Partitioning for Low Power Using Energy Estimation and Bounds

Optimal FSMD Functional Partitioning for Low Power

Optimal Fsmd Partitioning for Low Power

It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achiev...

Finite State Machines with Datapath

Resent investigations have shown the very good results of digital systems and circuits optimization using integration of dynamic power management in the design flow. This approach proceed from detection periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal. In this work, we take this approach to ...

Grid Impedance Estimation Using Several Short-Term Low Power Signal Injections

In this paper, a signal processing method is proposed to estimate the low and high-frequency impedances of power systems using several short-term low power signal injections for a frequency range of 0-150 kHz. This frequency range is very important, and thusso it is considered in the analysis of power quality issues of smart grids. The impedance estimation is used in many power system applicati...

Stacked FSMD : A New Microarchitecture Model for High - Level Synthesis

High-Level synthesis is a process that automates the transformation of an algorithmic description of a digital design into its physical implementation. With digital systems’ ever increasing complexity in terms of transistor count and clock speed, it becomes necessary for a high-level synthesis tool to work at higher levels of abstraction in order to effectively cope with the design. Traditional...